The transmission of data is an important function enabled by integrated circuits. A phase interpolator, which is sometimes referred to as a mixer, is a key component of a clock and data recovery (CDR) circuit. A CDR circuit implements a control loop that can adjust the data sampling clock to sample the data at the center of the data eye. The linearity of the phase interpolator is a key component in determining the CDR system performance. An analog current mode logic (CML) phase interpolator receives differential CML quadrature clocks and mixes them together in a controlled ratio to generate an output clock that has a controlled phase offset from the differential CML quadrature clocks. The phase of the output clock can cover a full 360 degree rotation.
A phase interpolator can be implemented to cover a wide range of input frequencies, such as between 2 GHz and 18 GHz. A phase interpolator can use different programmable power consumption settings that usually relate to the operating frequency, where higher operating frequencies generally require higher power to achieve the necessary bandwidth (i.e. gain at the output of the CML stage). The traditional load for CML phase interpolator is a passive resistor. However, the use of a passive resistor load in a phase interpolator has a number of drawbacks.
Accordingly, circuits and methods that implement a phase interpolator that provides greater bandwidth and lower power consumption are beneficial.